1. Field of the Invention
The present invention relates to semiconductor packages and to the leadframes encapsulated therein, and, more particularly, but not by way of limitation, to a leadframe for semiconductor packages which exhibits improved solder joint strength upon being mounted to a motherboard.
2. History of Related Art
It is conventional in the electronic industry to encapsulate one or more semiconductor devices, such as integrated circuit dies, or chips, in a semiconductor package. These plastic packages protect a chip from environmental hazards, and provide a method of and apparatus for electrically and mechanically attaching the chip to an intended device. Recently, such semiconductor packages have included metal leadframes for supporting an integrated circuit chip which is bonded to a chip paddle region formed centrally therein. Bond wires which electrically connect pads on the integrated circuit chip to individual leads of the leadframe are then incorporated. A hard plastic encapsulating material, or encapsulant, which covers the bond wire, the integrated circuit chip and other components, forms the exterior of the package. A primary focus in this design is to provide the chip with adequate protection from the external environment in a reliable and effective manner.
As set forth above, the semiconductor package therein described incorporates a leadframe as the central supporting structure of such a package. A portion of the leadframe completely surrounded by the plastic encapsulant is internal to the package. Portions of the leadframe extend internally from the package and are then used to connect the package externally. More information relative to leadframe technology may be found in Chapter 8 of the book Micro Electronics Packaging Handbook, (1989), edited by R. Tummala and E. Rymaszewski. This book is published by Van Nostrand Reinhold, 115 Fifth Avenue, New York, N.Y.
Once the integrated circuit chips have been produced and encapsulated in semiconductor packages described above, they may be used in a wide variety of electronic appliances. The variety of electronic devices utilizing semiconductor packages has grown dramatically in recent years. These devices include cellular phones, portable computers, etc. Each of these devices typically include a motherboard on which a significant number of such semiconductor packages are secured to provide multiple electronic functions. These electronic appliances are typically manufactured in reduced sizes and at reduced costs, as consumer demand increases. Accordingly, not only are semiconductor chips highly integrated, but also semiconductor packages are highly miniaturized with an increased level of package mounting density.
According to such miniaturization tendencies, semiconductor packages, which transmit electrical signals from semiconductor chips to motherboards and support the semiconductor chips on the motherboards, have been designed to have a small size. By way of example only, such semiconductor packages may have a size on the order of 1×1 mm to 10×10 mm.
In further description of the above-described semiconductor package design aspects, reference is now made to FIGS. 1–3 where a prior art leadframe 100 and semiconductor package 200 are shown. Referring specifically now to FIG. 1, a typical prior art leadframe 100 is shown and described. The leadframe 100 has a plate-type frame body 120 with an opening 125 at its center and a chip paddle 110 located within the opening 125 on which a semiconductor chip (not shown) is subsequently mounted. About the perimeter of the chip paddle 110 and extending inwardly from the frame body 120 toward the opening 125, a plurality of internal leads 130 are located radially and spaced at regular intervals. The chip paddle 110 is connected to the frame body 120 by tie bars 150 which may be extended inwardly from the ends of at least two internal leads 130, as shown here, or from the frame body 120 itself. The internal leads 130 extend outward into external leads 135 which are in turn made integral to the frame body 120. Dam bars 140 are provided to separate the internal leads 130 from the external leads 135 during the encapsulation process and to prevent encapsulation material (not shown) from covering the external leads 135. It is particularly notable that in the prior art leadframe 100, each of the internal leads 130 are all substantially the same length L.
Referring still to FIG. 1, the reference numerals 111, 131 and 151 denote half-etched portions of chip paddle 110, the internal leads 130 and the tie bars 150, respectively. These half-etched portions will generally be about half as thick as the remainder of the part. During the subsequent encapsulation process for forming a semiconductor package, encapsulation material flows under these portions of the part to ensure a better seal for the internal components.
Referring now to FIG. 2, a semiconductor package 200 using the prior art leadframe 100 is presented. As shown, the semiconductor package 200 includes a semiconductor chip 105 having a plurality of bond pads or input/output pads 106 on its upper surface along its perimeter, and a chip paddle 110 which is bonded to the bottom surface of the semiconductor chip 105 via an adhesive. The chip paddle 110 also features a half-etched portion 111 along its perimeter. A plurality of internal leads 130, each of which has a half-etched portion (not shown) are radially located about the perimeter of the chip paddle 110. The input/output pads 106 of the semiconductor chip 105 are electrically connected to the internal leads 130 via conductive wires 115. As shown here, the semiconductor chip 105, the chip paddle 110, the internal leads 130, and the conductive wires 115, are all sealed within an encapsulation material 10 to create a semiconductor package 200. Referring back to FIG. 1, the external portions of the leadframe 100, namely the dam bars 140 and the external leads 135, which are not encapsulated are then trimmed off. The tie bars 150 may also be cut or singulated following encapsulation to completely separate the chip paddle 110 from the frame body 120.
Referring now to FIG. 3, note that following encapsulation, the chip paddle 110, the internal leads 130, and the tie bars 150 remain externally exposed on the underside of the semiconductor package 200. The semiconductor package 200 is subsequently placed in electrical communication with the host device by fusing or soldering the exposed bottom surfaces or lands of the internal leads 130 to a motherboard (not shown).
Referring still to FIG. 3, the internal leads 130 on the underside of the semiconductor package 200 are regularly spaced at a distance G1 from each other. The internal leads 130 are all of substantially the same length L and are arranged at regular distances G1 to prevent the internal leads 130 which are closest to the corners from forming a short circuit upon soldering. Typically, the internal leads will have a fixed length L of about 0.4 mm to 0.6 mm. Unfortunately, as the other internal leads 130 which are not located near the corners are formed at the same length, the resulting semiconductor package 200 will typically exhibit very poor solder joint strength at the interface with the motherboard. Solder joint strength tends to vary proportionally with the amount of surface area placed in direct contact with the motherboard. Consequently, a lead having a larger surface area should exhibit greater solder joint strength than a lead with a smaller surface area.